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Keywords

ANFIS Bell, shaped fuzzy set Membership Function Hardware resources minimization FPGA

Document Type

Research Paper

Abstract

The complexity of hardware realization for the Bell function forces most researchers to replace it with trapezoidal, negatively affecting accuracy. The implementation complexity of the Bell function on FPGA comes from bundling the division operator by FPGA. This requires large hardware resources due to the limited number of logic elements in FPGA devices, such as Lock-Up Tables (LUTs), slices, and DSP48 units, specifically when utilizing the Spartan-3A DSP sc3sd3400a Xilinx FPGA kit. This work investigates hardware resource minimization of Bell Membership Functions (MFs) based on FPGA implementation. A comparative analysis of seven proposed designs with a predesigned system is studied, focusing on resource utilization and performance evaluation. Approach 1 uses the highest number of DSP48 blocks (10). Conversely, Approach 7 achieves the highest area minimization, using the least number of slices (79) and LUTs (144) with zero DSP48 blocks with a reduction rate equal to (97.7%) for slices and (96.7%) LUTs regarding previous work. The absence of multiplication blocks for implementing Approach 7 comes from modifying the precomputation method using half memory size. Performance evaluation indicates varying error rates of 1.06%, 1.14%, and 1.16% for Approaches 1, 2, and 3, respectively. Approaches 6 and 7 exhibit the lowest error rates (0.17%), suggesting superior accuracy, including the previous work. To sum up, the modification in Approach 7 is a very useful method that reduces the hardware platform area and enhances the performance. Thus, this approach is adopted as the best method for designing the Bell function by FPGA.

References

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Highlights

The importance of optimizing Bell membership function designs for FPGA implementations was highligted. Seven approaches are proposed to reduce the hardware required for Bell function implementation on FPGA devices. Resource use, performance, and power are analyzed for Bell function designs on a Spartan-3A DSP FPGA kit. The polynomial curve fitting method is segmented to lower equation order and reduce hardware needed for Bell function.

DOI

10.30684/etj.2024.151873.1786

First Page

137

Last Page

148

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